The present invention generally relates to vertical synchronizing signal separating circuits, and more particularly to a vertical synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal by use of digital circuits.
As circuits for separating a vertical synchronizing signal from a composite synchronizing signal, there conventionally are circuits employing an analog system and circuits employing a digital system. The conventional vertical synchronizing signal separating circuit employing the analog system comprises a lowpass filter for filtering a vertical synchronizing signal frequency of the composite synchronizing signal and a pulse amplifier for shaping and amplifying an output signal of the lowpass filter so as to produce the vertical synchronizing signal. On the other hand, the conventional vertical synchronizing signal employing the digital system comprises an up-down counter. For example, the up-down counter counts up when the composite synchronizing signal has a high level and counts down when the composite synchronizing signal has a low level, and the vertical synchronizing signal is separated from the composite synchronizing signal by use of a counted value in the up-down counter.
However, in the case of the conventional vertical synchronizing signal separating circuit employing the analog system, there is a need to provide a capacitor because the lowpass filter is used. As a result, because of the need to provide the capacitor, it is difficult to produce the entire circuit in the form of an integrated circuit. In addition, there is a problem in that a time required for the detection of the vertical synchronizing signal changes depending on a voltage level of the composite synchronizing signal.
On the other hand, in the case of the conventional vertical synchronizing signal separating circuit employing the digital system, the up-down counter is generally constituted by a large number of circuit elements and is designed to count clock pulses. However, since the composite synchronizing signal and the clock pulses are not in synchronism with each other, there is a problem in that a jitter is generated by the clock pulses which are counted in the up-down counter.